1. Field of the Invention
The present invention relates to a transistor, and more particularly to a field-effect transistor and a manufacturing method thereof, in which a separate lithography process and its corresponding additional process are not required, and insulating films below field electrodes have different thicknesses.
2. Description of the Prior Art
FIGS. 1A to 1H are views illustrating a method for manufacturing a field-effect transistor, according to a prior art.
As shown in FIG. 1A, on a semiconductor substrate 10 including gallium nitride (GaN), silicon (Si), silicon carbide (SiC), semi-insulating gallium arsenide (GaAs), etc., an active layer 11 and a cap layer 12 are sequentially formed. For example, in a case of a high electron mobility transistor (HEMT) element using hetero junction of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), the active layer 11 includes a gallium nitride buffer layer and an aluminum gallium nitride barrier layer, and the cap layer 12 includes a gallium nitride (GaN) layer.
As shown in FIG. 1B, a region where a source•drain ohmic metal layer 13 is to be formed is defined as a source•drain pattern. On the upper surface of the cap layer 12, an ohmic metal is deposited and then the source•drain ohmic metal layer 13 is formed through rapid thermal annealing (RTA), etc. For example, in a manufacturing process of an HEMT element using a gallium nitride (GaN)-based compound semiconductor, as an ohmic metal, a metal layer formed by sequentially depositing a Ti film, an Al film, a Ni film, an Au film, etc. with a predetermined thickness is used. In a process of manufacturing an HEMT element, a metal semi-conductor field effect transistor (MESFET), or the like by using a gallium arsenide (GaAs)-based compound semiconductor, a metal layer formed by sequentially depositing an AuGe film, a Ni film, an Au film, etc. with a predetermined thickness is used as an ohmic metal.
As shown in FIG. 1C, on the cap layer 12 which has been subjected to an ohmic process, a photosensitive film is coated, and then gate patterns 14a, 14b and 14c formed with a T-shaped hole 15a are formed by using optical lithography, e-beam lithography or the like. Herein, the gate patterns 14a, 14b and 14c are used to manufacture a T-shaped gate electrode while reducing a gate width without an increase in a resistance of a gate electrode.
As shown in FIG. 1D, a gate recess process for etching the cap layer 12 exposed through the T-shaped hole 15a is performed so as to form a gate recess region 15b to be deposited with a gate metal. Herein, the gate recess process is the most critical step in manufacturing of an HEMT element or an MESFET element using a compound semiconductor, and is generally performed while measuring a current. Also, the process includes one or more steps including a wet process, a dry process or a combination of the wet and dry processes. The gate recess process is performed using a gas such as CF4, BCl3, Cl2 and SF6 in an apparatus for dry etching such as an electron cyclotron resonance (ECR) or inductive coupled plasma (ICP). Herein, the process is carried out by using various wet etching solutions such as a phosphoric acid-based solution in which H3PO4, H2O2 and H2O applied to a gallium arsenide (GaAs)-based compound semiconductor element are mixed at a predetermined ratio.
As shown in FIG. 1E, a gate metal is deposited on the gate patterns 14a, 14b, and 14c, and the gate patterns 14a, 14b, and 14c are removed by a lift-off process, thereby forming a T-shaped gate electrode 16. For example, in the manufacturing process of the HEMT element using a gallium nitride (GaN)-based compound semiconductor, the gate electrode 16 is formed by sequentially depositing metal layers such as a Ni film, and an Au film to a predetermined thickness. In the manufacturing process of an HEMT element, an MESFET element, or the like using a gallium arsenide (GaAs)-based compound semiconductor, the gate electrode 16 is formed by sequentially depositing metal layers such as a Ti film, a Pt film, an Au film, etc. to a predetermined thickness.
As shown in FIG. 1F, after the gate electrode 16 is formed, on the cap layer 12's upper portion including the source•drain ohmic metal layer 13 and the T-shaped gate electrode 16, an insulating film 17 is deposited. Then, as shown in FIG. 1G, through the performance of a lithography process for forming a field electrode, a field electrode pattern 18 is formed.
As shown in FIG. 1H, after a metal is deposited on the field electrode pattern 18 for forming a field electrode, and the field electrode pattern 18 is removed by a lift-off process, thereby forming a plurality of field electrodes 19. In this case, for the plurality of field electrodes 19, the thickness of the insulating film 17 below the field electrodes 19 is fixed as a predetermined thickness. In a case where the thickness of the insulating film 17 below each of the field electrodes 19 is adjusted, a separate mask pattern for each of the field electrodes 19 is required and thus, a lithography process, an etching process, a metal-deposition process and a lift-off process are performed.
As described above, in a case of a conventional field-effect transistor including a field electrode, and a manufacturing method thereof, in manufacturing of the field electrode, a peak value may be reduced through field reduction in a region of a gate and a drain. Furthermore, it is possible to achieve a high breakdown voltage through a reduction of leakage current of a gate while maintaining high frequency performance and also it is expected that it is possible to reduce a capacitance between a gate and a drain through a shielding effect. Accordingly, it is possible to manufacture a power device which is capable of being driven at high voltage and high current.
However, in the case of a field-effect transistor including a field electrode, the thickness of an insulating film below field electrodes on one substrate is generally fixed. Thus, in order to adjust the thickness of the insulating film, a separate mask pattern is required for each of the field electrodes. Furthermore, for respective mask patterns, a lithography process, an etching process, a metal-deposition process, and a lift-off process have to be repeatedly performed.
For example, in an HEMT element manufactured using a compound semiconductor including GaN, GaAs, InP, etc., one or more field electrodes, besides a gate, are manufactured between a source and a drain. In the field electrodes manufactured using a mask pattern for forming the field electrodes, the thickness of an insulating film below the field electrodes on one substrate is generally fixed. Thus, in order to adjust the thickness of the insulating film below each of the field electrodes, a separate mask pattern is required for each of the field electrodes. Furthermore, for respective mask patterns, a lithography process, an etching process, a metal-deposition process, and a lift-off process have to be repeatedly performed.
Accordingly, in a case of a conventional manufacturing method of a field-effect transistor including a field electrode, it is impossible to apply different thicknesses of an insulating film below field electrodes, to the same element. Even when the thickness of an insulating film below field electrodes can be varied, a separate mask pattern is required for each of the field electrodes. Furthermore, for respective mask patterns, a lithography process, an etching process, a metal-deposition process and a lift-off process have to be repeatedly performed. This causes a problem such as an increase in a unit cost of a manufacturing process and a reduction of productivity.